NXP Semiconductors /LPC43xx /SCU /SFSCLK_0

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Interpret as SFSCLK_0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FUNCTION_0_DEFAULT)MODE0 (DISABLE_PULL_DOWN)EPD 0 (ENABLE_PULL_UP)EPUN 0 (FAST_LOW_NOISE_WITH)EHS 0 (DISABLE_INPUT_BUFFER)EZI 0 (ENABLE_INPUT_FILTER)ZIF 0RESERVED

EPD=DISABLE_PULL_DOWN, ZIF=ENABLE_INPUT_FILTER, EZI=DISABLE_INPUT_BUFFER, EHS=FAST_LOW_NOISE_WITH, EPUN=ENABLE_PULL_UP, MODE=FUNCTION_0_DEFAULT

Description

Pin configuration register for pins CLK

Fields

MODE

Select pin function.

0 (FUNCTION_0_DEFAULT): Function 0 (default)

1 (FUNCTION_1): Function 1

2 (FUNCTION_2): Function 2

3 (FUNCTION_3): Function 3

4 (FUNCTION_4): Function 4

5 (FUNCTION_5): Function 5

6 (FUNCTION_6): Function 6

7 (FUNCTION_7): Function 7

EPD

Enable pull-down resistor at pad.

0 (DISABLE_PULL_DOWN): Disable pull-down.

1 (ENABLE_PULL_DOWN): Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode.

EPUN

Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.

0 (ENABLE_PULL_UP): Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.

1 (DISABLE_PULL_UP): Disable pull-up.

EHS

Slew rate

0 (FAST_LOW_NOISE_WITH): Fast (low noise with fast speed)

1 (HIGH_SPEED_MEDIUM_N): High-speed (medium noise with high speed)

EZI

Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.

0 (DISABLE_INPUT_BUFFER): Disable input buffer

1 (ENABLE_INPUT_BUFFER): Enable input buffer

ZIF

Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.

0 (ENABLE_INPUT_FILTER): Enable input filter

1 (DISABLE_INPUT_FILTER): Disable input filter

RESERVED

Reserved

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